20.13.3 TxCLK

Timer Clock Source Selection Register
Name: TxCLK
Offset: 0x0291,0x0297

Bit 76543210 
    CS[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 20-4. Timer Clock Sources
CSClock Source
Timer1Timer3
11111-10001Reserved
10000CLC4_OUT
01111CLC3_OUT
01110CLC2_OUT
01101CLC1_OUT
01100TMR3_overflowReserved
01011ReservedTMR1_overflow
01010TMR0_overflow
01001EXTOSC
01000SOSC
00111MFINTOSC (32 kHz)
00110MFINTOSC (500 kHz)
00101SFINTOSC (1 MHz)
00100LFINTOSC
00011HFINTOSC
00010FOSC
00001FOSC/4
00000Pin selected by T1CKIPPSPin selected by T3CKIPPS
Reset States: 
POR/BOR = 00000
All Other Resets = uuuuu