10.10 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS, PCON0 and PCON1 registers are updated to indicate the cause of the Reset. The following tables show the Reset conditions of these registers.

Table 10-3. Reset Status Bits and Their Significance
STKOVFSTKUNFRWDTRMCLRRIPORBORTOPDMEMVCondition
001110x111Power-on Reset
001110x0xuIllegal, TO is set on POR
001110xx0uIllegal, PD is set on POR
00u11u011uBrown-out Reset
uu0uuuu0uuWDT Reset
uuuuuuu00uWDT Wake-up from Sleep
uuuuuuu10uInterrupt Wake-up from Sleep
uuu0uuuuu1MCLR Reset during normal operation
uuu0uuu10uMCLR Reset during Sleep
uuuu0uuuuuRESET Instruction Executed
1uuuuuuuuuStack Overflow Reset (STVREN = 1)
u1uuuuuuuuStack Underflow Reset (STVREN = 1)
uuuuuuuuu0Memory Violation Reset
Table 10-4. Reset Conditions for Special Registers
ConditionProgram CounterSTATUS RegisterPCON0 RegisterPCON1 Register
Power-on Reset0---1 10000011 110x---- --1-
Brown-out Reset0---1 10000011 11u0---- --u-
MCLR Reset during normal operation0-uuu uuuuuuuu 0uuu---- --1-
MCLR Reset during Sleep0---1 0uuuuuuu 0uuu---- --u-
WDT Time-out Reset0---0 uuuuuuu0 uuuu---- --u-
WDT Wake-up from SleepPC + 1---0 0uuuuuuu uuuu---- --u-
Interrupt Wake-up from SleepPC + 1(1)---1 0uuuuuuu uuuu---- --u-
RESET Instruction Executed0---u uuuuuuuu u0uu---- --u-
Stack Overflow Reset (STVREN = 1)0---u uuuu1uuu uuuu---- --u-
Stack Underflow Reset (STVREN = 1)0---u uuuuu1uu uuuu---- --u-
Memory Violation Reset0-uuu uuuuuuuu uuuu---- --0-

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.

Note:
  1. When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.