36.10.1 ZCDCON
| Name: | ZCDCON |
| Offset: | 0x101F |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SEN | OUT | POL | INTP | INTN | |||||
| Access | R/W | R | R/W | R/W | R/W | ||||
| Reset | 0 | x | 0 | 0 | 0 |
Bit 7 – SEN Zero-Cross Detect Software Enable
This bit is ignored when the ZCD fuse is cleared.
| Value | Name | Description |
|---|---|---|
X |
ZCD Config fuse =
0 |
Zero-cross detect is always enabled. This bit is ignored. |
1 |
ZCD Config fuse =
1 |
Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. |
0 |
ZCD Config fuse =
1 |
Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. |
Bit 5 – OUT Zero-Cross Detect Data Output
| Value | Name | Description |
|---|---|---|
1 |
POL = 0 |
ZCD pin is sinking current |
0 |
POL = 0 |
ZCD pin is sourcing current |
1 |
POL = 1 |
ZCD pin is sourcing current |
0 |
POL = 1 |
ZCD pin is sinking current |
Bit 4 – POL Zero-Cross Detect Polarity
| Value | Description |
|---|---|
1 |
ZCD logic output is inverted |
0 |
ZCD logic output is not inverted |
Bit 1 – INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable
| Value | Description |
|---|---|
1 |
The ZCDIF bit is set on low-to-high ZCD_output transition |
0 |
The ZCDIF bit is unaffected by low-to-high ZCD_output transition |
Bit 0 – INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable
| Value | Description |
|---|---|
1 |
The ZCDIF bit is set on high-to-low ZCD_output transition |
0 |
The ZCDIF bit is unaffected by high-to-low ZCD_output transition |