15.2.2.2 NVM Unlock Sequence

The unlock sequence is a mechanism that protects the DFM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete an erase or write operation.

The unlock sequence consists of the following steps and must be completed in order:

  • Write 55h to NVMCON2
  • Write AAh to NMVCON2
  • Set the WR bit

Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction.

Since the unlock sequence must not be interrupted, global interrupts must be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

Figure 15-9. NVM Unlock Sequence

NVM Unlock Sequence

NVMCON1bits.WREN = 1;          // Enable write/erase
INTCONbits.GIE = 0;            // Disable global interrupts

// The next three steps are the required unlock sequence
NVMCON2 = 0x55;                // First unlock code
NVMCON2 = 0xAA;                // Second unlock code
NVMCON1bits.WR = 1;            // Initiate write/erase cycle

INTCONbits.GIE = 1;            // Enable global interrupts
NVMCON1bits.WREN = 0;          // Disable further write/erase cycles
Note: Sequence begins when NVMCON2 is written; the three unlock steps must occur in the cycle-accurate order shown. If the timing of the sequence is corrupted by an interrupt or a debugger Halt, the action will not take place.