21.7 Operating Modes
Mode | MODE | Output Operation | Operation | Timer Control | |||
---|---|---|---|---|---|---|---|
[4:3] | [2:0] | Start | Reset | Stop | |||
Free-Running Period | 00 | 000 | Period Pulse | Software gate (Figure 21-3) | ON =
1 | — | ON =
0 |
001 | Hardware gate, active-high | ON =
1 andTMRx_ers =
| — | ON =
0 orTMRx_ers =
| |||
010 | Hardware gate, active-low | ON =
1 andTMRx_ers =
| — | ON =
0 orTMRx_ers =
| |||
011 |
Period Pulse with Hardware Reset | Rising or falling edge Reset | ON = 1 | TMRx_ers ↕ | ON = 0 | ||
100 | Rising edge Reset (Figure 21-5) | TMRx_ers ↑ | |||||
101 | Falling edge Reset | TMRx_ers ↓ | |||||
110 | Low-level Reset | TMRx_ers
= 0 | ON =
0 orTMRx_ers =
| ||||
111 | High-level Reset (Figure 21-6) | TMRx_ers
= 1 | ON =
0 orTMRx_ers =
| ||||
One Shot | 01 | 000 | One-shot | Software start (Figure 21-7) | ON =
1 | — | ON = 0 or Next clock after TxTMR = TxPR (Note 2) |
001 |
Edge-Triggered Start (Note 1) | Rising edge start (Figure 21-8) | ON =
1 andTMRx_ers ↑ | — | |||
010 | Falling edge start | ON =
1 andTMRx_ers ↓ | — | ||||
011 | Any edge start | ON =
1 andTMRx_ers ↕ | — | ||||
100 |
Edge-Triggered Start and Hardware Reset (Note 1) | Rising
edge start and Rising edge Reset (Figure 21-9) | ON =
1 andTMRx_ers ↑ | TMRx_ers ↑ | |||
101 | Falling
edge start and Falling edge Reset | ON =
1 andTMRx_ers ↓ | TMRx_ers ↓ | ||||
110 | Rising
edge start and Low-level Reset (Figure 21-10) | ON =
1 andTMRx_ers ↑ | TMRx_ers
= 0 | ||||
111 | Falling
edge start and High-level Reset | ON =
1 andTMRx_ers ↓ | TMRx_ers
= 1 | ||||
Monostable | 10 | 000 | Reserved | ||||
001 |
Edge-Triggered Start (Note 1) | Rising edge start | ON =
1 andTMRx_ers ↑ | — | ON = 0 or Next clock after TxTMR = TxPR (Note 3) | ||
010 | Falling edge start | ON =
1 andTMRx_ers ↓ | — | ||||
011 | Any edge start | ON =
1 andTMRx_ers ↕ | — | ||||
Reserved | 100 | Reserved | |||||
Reserved | 101 | Reserved | |||||
One Shot | 110 |
Level-Triggered Start and Hardware Reset | High-level start and Low-level Reset (Figure 21-12) | ON =
1 andTMRx_ers =
| TMRx_ers
= 0 | ON = 0 orHeld in Reset (Note 2) | |
111 | Low-level start and High-level Reset | ON =
1 andTMRx_ers = | TMRx_ers
= 1 | ||||
Reserved | 11 | xxx | Reserved |
- If ON =
0
, then an edge is required to restart the timer after ON =1
. - When T2TMR = T2PR, the next clock
clears ON and stops T2TMR at
00h
. - When T2TMR = T2PR, the next clock
stops T2TMR at
00h
but does not clear ON.