21.10.4 TxHLT
Note:
- Setting this bit ensures that reading TxTMR will return a valid data value.
- When this bit is ‘
1
’, the Timer cannot operate in Sleep mode. - CKPOL must not be changed while ON =
1
. - Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
- When this bit is set, then the timer operation will be delayed by two input clocks after the ON bit is set.
- Unless otherwise indicated, all modes start upon ON =
1
and stop upon ON =0
(stops occur without affecting the value of TxTMR). - When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.
Name: | TxHLT |
Offset: | 0x030F,0x0315,0x031B |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PSYNC | CPOL | CSYNC | MODE[4:0] | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – PSYNC Timer Prescaler Synchronization Enable(1, 2)
Value | Description |
---|---|
1 |
Timer Prescaler Output is synchronized to FOSC/4 |
0 |
Timer Prescaler Output is not synchronized to FOSC/4 |
Bit 6 – CPOL Timer Clock Polarity Selection(3)
Value | Description |
---|---|
1 |
Falling edge of input clock clocks timer/prescaler |
0 |
Rising edge of input clock clocks timer/prescaler |
Bit 5 – CSYNC Timer Clock Synchronization Enable(4, 5)
Value | Description |
---|---|
1 |
ON bit is synchronized to timer clock input |
0 |
ON bit is not synchronized to timer clock input |
Bits 4:0 – MODE[4:0] Timer Control Mode Selection(6, 7)
Value | Description |
---|---|
00000 to
11111 |
See Table 21-1 |