29.4.4 SSPxSTAT
Note:
- This bit is cleared on Reset and when SSPEN is cleared.
- In I2C Client mode, this bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit.
- ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
- Polarity of clock state is set by the CKP bit.
- I2C receive status does not include ACK and Stop bits.
Name: | SSPxSTAT |
Offset: | 0x068F,0x0699 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SMP | CKE | D/A | P | S | R/W | UA | BF | ||
Access | R/W | R/W | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SMP Slew Rate Control bit
Value | Name | Description |
---|---|---|
1 | SPI Host | Input data is sampled at the end of data output time |
0 | SPI Host | Input data is sampled at the middle of data output time |
0 | SPI Client | Bit must be cleared in SPI Client mode |
1 | I2C | Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) |
0 | I2C | Slew rate control is enabled for High Speed mode (400 kHz) |
Bit 6 – CKE SPI: Clock Select bit(4); I2C: SMBus Select bit
Value | Name | Description |
---|---|---|
1 | SPI | Transmit occurs on the transition from Active to Idle clock state |
0 | SPI | Transmit occurs on the transition from Idle to Active clock state |
1 | I2C | Enables SMBus-specific inputs |
0 | I2C | Disables SMBus-specific inputs |
Bit 5 – D/A Data/Address bit
Value | Name | Description |
---|---|---|
x | SPI or I2C Host | This bit is not used |
1 | I2C Client |
Indicates that the last byte received or transmitted was data |
0 | I2C Client |
Indicates that the last byte received or transmitted was address |
Bit 4 – P Stop bit(1)
Value | Name | Description |
---|---|---|
x | SPI | This bit is not used |
1 | I2C | Stop bit was detected last |
0 | I2C | Stop bit was not detected last |
Bit 3 – S Start bit(1)
Value | Name | Description |
---|---|---|
x | SPI | This bit is not used |
1 | I2C | Start bit was detected last |
0 | I2C | Start bit was not detected last |
Bit 2 – R/W Read/Write Information bit(2,3)
Value | Name | Description |
---|---|---|
x | SPI | This bit is not used |
1 | I2C Client | Read |
0 | I2C Client | Write |
1 | I2C Host | Transmit is in progress |
0 | I2C Host | Transmit is not in progress |
Bit 1 – UA Update Address bit (10-bit I2C Client mode only)
Value | Name | Description |
---|---|---|
x | All other modes | This bit is not used |
1 | I2C 10-bit Client | Indicates that the user needs to update the address in the SSPxADD register |
0 | I2C 10-bit Client | Address does not need to be updated |
Bit 0 – BF Buffer Full Status bit(5)
Value | Name | Description |
---|---|---|
1 | I2C Transmit | Transmit in progress, SSPxBUF is full |
0 | I2C Transmit | Transmit complete; SSPxBUF is empty |
1 | SPI and I2C Receive | Receive complete, SSPxBUF is full |
0 | SPI and I2C Receive | Receive not complete, SSPxBUF is empty |