28.6.6 PIT64B Interrupt Disable Register
This register can only be written if the WPITEN bit is cleared in the PIT64B Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt
Name: | PIT64B_IDR |
Offset: | 0x14 |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | SECE | | | OVRE | PERIOD | |
Access | | | | W | | | W | W | |
Reset | | | | – | | | – | – | |
Bit 4 – SECE Safety and/or Security Report Interrupt Disable
Bit 1 – OVRE Overrun Error Interrupt Disable
Bit 0 – PERIOD Elapsed Timer Period Interrupt Disable