28.6.2 PIT64B Mode Register
This register can only be written if the WPEN bit is cleared in the PIT64B Write Protection Mode Register.
When the timer is running, writing a value to this register has no effect. The value written is this register is loaded anytime before a START command is issued.
Name: | PIT64B_MR |
Offset: | 0x04 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PRESCALER[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SMOD | SGCLK | CONT | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bits 11:8 – PRESCALER[3:0] Prescaler Period
Value | Description |
---|---|
0 | A prescaler divider of 1 is used. |
1-15 | The 64-bit timer is incremented at each (PRESCALER+1)x selected period (see SGCLK). |
Bit 4 – SMOD Start Mode
Value | Description |
---|---|
0 |
Writing PIT64B_LSBPR does not start the timer period. |
1 |
Writing PIT64B_LSBPR starts the timer period. |
Bit 3 – SGCLK Generic Clock Selection Enable
Value | Description |
---|---|
0 | The prescaler is triggered at each rising edge of “Peripheral clock” and the timer is triggered. |
1 | GCLK clock is selected as clock source of the 8-bit prescaler. |
Bit 0 – CONT Continuous Mode
Value | Description |
---|---|
0 | A single period interrupt is generated from a START command. |
1 | Continuous periodic interrupts are generated after a single START command. |