28.6.7 PIT64B Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
Name: | PIT64B_IMR |
Offset: | 0x18 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | SECE | | | OVRE | PERIOD | |
Access | | | | R | | | R | R | |
Reset | | | | 0 | | | 0 | 0 | |
Bit 4 – SECE Safety and/or Security Report Interrupt Mask
Bit 1 – OVRE Overrun Error Interrupt Mask
Bit 0 – PERIOD Elapsed Timer Period Interrupt Mask