Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the QSPI Serial Clock register (QSPI_SCR). QSPI_SCR.CPHA programs the clock phase. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of these parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, the interfaced client must use the same parameter values to communicate.
The table below shows the four modes and the corresponding parameter settings.
Table 64-2. QSPI Bus Clock Modes
QSPI Clock Mode
QSPI_SCR.CPOL
QSPI_SCR.CPHA
Shift QSCK Edge
Capture QSCK Edge
QSCK Inactive Level
0
0
0
Falling
Falling
Low
1
0
1
Rising
Rising
Low
2
1
0
Rising
Rising
High
3
1
1
Falling
Falling
High
The figures below show examples of data transfers.Figure 64-4. QSPI Transfer Format (QSPI_SCR.CPHA=0, 8 bits per
transfer)
Figure 64-5. QSPI Transfer Format (QSPI_SCR.CPHA=1, 8 bits per transfer)
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