64.6.1 Register Synchronization

As the Quad Serial Peripheral Interface and the QSPI Controller core use different clocks, the following events must be synchronized with the core after being configured:

  • QSPI_CR.QSPIEN
  • QSPI_CR.QSPIDIS
  • QSPI_CR.SRFRSH
  • QSPI_CR.SWRST
  • QSPI_CR.UPDCFG
  • QSPI_CR.STTFR
  • QSPI_CR.RTOUT
  • QSPI_CR.LASTXFER
  • QSPI_RDR.RD (synchronization only when QSPI_MR.SMM is set to ‘1 ‘)
  • QSPI_TDR.TD
  • QSPI_WRACNT.NBWRA

Before accessing any of these bits/fields, check that the SYNCBSY bit in the Status register (QSPI_SR) is at 0 to ensure that no synchronization process is ongoing.

When synchronization is in progress, SYNCBSY is at 1.

As long as SYNCBSY is at 1, no access to the registers requiring synchronization is allowed.

When using UPDCFG in the Control register (QSPI_CR) to update the system configuration, SYNCBSY must be at 0 before and after writing UPDCFG. This ensures that the update is completed before going on to the next step.

Note: If the TDRE or RDRF flag is checked, checking QSPI_SR.SYNCBSY for QSPI_RDR.RD and QSPI_TDR.TD is not necessary. See Figure 64-13, Figure 64-15 and Figure 64-18 for detailed procedures.
Figure 64-2. Register Synchronization with QSPI Controller Core