64.6.4 Transfer Delays

Figure 64-6 and Figure 64-7 show several consecutive transfers while the chip select is active. Three delays can be programmed to modify the transfer waveforms:

• The delay between the deactivation and the activation of QCS, programmed by writing QSPI_MR.DLYCS—to adjust the minimum time of QCS at high level.
• The delay before QSCK, programmed by writing QSPI_SCR.DLYBS—to start delaying QSCK after the chip select has been asserted.
• The delay between consecutive transfers, programmed by writing QSPI_MR.DLYBCT.
  • QSPI_MR.SMM=0, to insert a delay between two consecutive transfers
  • QSPI_MR.SMM=1, to insert a delay between the last QSCK pulse and the QCS rise.
• The delay between consecutive transfers when SMM=1, programmed by writing QSPI_SCR.DLYBCT.

These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time.