45.6.10.1 Dedicated Registers

When a new data word is available in I2SMCC_RHLxR, the corresponding I2SMCC_ISRA.RXLRDYx is set. Reading I2SMCC_RHLxR clears this bit. When a new data word is available in I2SMCC_RHRxR, the corresponding I2SMCC_ISRA.RXRRDYx is set. Reading I2SMCC_RHRxR clears this bit.

A receive overrun condition occurs if a new data word becomes available for the left channel x before the previous data word has been read from I2SMCC_RHLxR. In this case, the Receive Left x Overrun bit (RXLOVFx) in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit. A receive overrun condition occurs if a new data word becomes available for the right channel x before the previous data word has been read from I2SMCC_RHRxR. In this case, the Receive Right x Overrun bit (RXROVFx) in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit.

When I2SMCC_THLxR is empty, I2SMCC_ISRA.TXLRDYx is set. Writing to I2SMCC_THLxR clears this bit. When I2SMCC_THRxR is empty, I2SMCC_ISRA.TXRRDYx is set. Writing to I2SMCC_THRxR clears this bit.

A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to I2SMCC_THLxR. In this case, the Transmit Left x Underrun (TXLUNFx) bit in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit. A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to I2SMCC_THRxR. In this case, the Transmit Right x Underrun (TXRUNFx) bit in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit.

In case of transmit underrun, if I2SMCC_MRA.TXSAME is ‘0’, then a zero data word is transmitted. If I2SMCC_MRA.TXSAME is ‘1’, then the previous data word for the current transmit channel number is transmitted.

Data words are right-justified in all dedicated registers (I2SMCC_RHLxR, I2SMCC_RHRxR, I2SMCC_THLxR and I2SMCC_THRxR). The 16-bit compact and 8-bit compact stereo data formats are not supported through dedicated registers.

In TDM or TDM Left-Justified mode, the dedicated left registers are used for even-numbered channels and the dedicated right registers are used for odd-numbered channels. The data of TDM channel 0 can be read through the I2SMCC_RHL0R and written through the I2SMCC_THL0R, the data of TDM channel 1 can be read through the I2SMCC_RHR0R and written through the I2SMCC_THR0R. Data read/write continues in this manner up to the data of TDM channel 6 read through the I2SMCC_RHL3R and written through the I2SMCC_THL3R and the data of TDM channel 7 read through the I2SMCC_RHR3R and written through the I2SMCC_THR3R.