45.6.10.2 Common Registers

The Receiver Holding Register (I2SMCC_RHR) and the Transmitter Holding Register (I2SMCC_THR) provide an access to all channels enabled through a single location.

When a new data word is available, the corresponding bit RXLRDYx or RXRRDYx in I2SMCC_ISRA is set. Reading I2SMCC_RHR clears this bit. In I²S or Left-Justified mode with the Common register Access Mode bit (CRAMODE) of the Mode register B (I2SMCC_MRB) set to ‘0’, consecutive access to I2SMCC_RHR reads first all the left channels enabled then all the right channels enabled. In I²S or Left-Justified mode with I2SMCC_MRB.CRAMODE set to ‘1’, consecutive access to I2SMCC_RHR reads first the left and right channels of the first , then the left and right channels of the second I²S enabled and so on until the last I²S enabled. In TDM or TDM Left-Justified mode, consecutive access to I2SMCC_RHR reads the TDM channels enabled.

When a receive overrun condition occurs, the corresponding bit RXLOVFx or RXROVFx in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit.

When the FIFO is disabled:

When data is being received (i.e., stored in the internal shift register), it is stored in internal holding registers. As an example, when 2-wire mode is configured, up to two data for each wire can be stored because four internal holding registers are available.

If nothing is read from I2SMCC_RHR, or from I2MCC_RHLxR and I2SMCC_RHRxR, the overflow occurs if a new data becomes available for the left channel x or right channel x.

When the FIFO is enabled:

When data is being received (i.e., stored in the internal shift register), it is transferred to internal holding registers and immediately stored in the FIFO.

If nothing is read from I2SMCC_RHR, once the FIFO is full, the new data are stored in internal holding registers (up to four).

Once these internal holding registers are full, a subsequent data is the triggering condition for the overflow.

When a data can be written in I2SMCC_THR, the corresponding bit TXLRDYx bit or TXRRDYx in I2SMCC_ISRA is set. Writing to I2SMCC_THR clears this bit. In I²S or Left-Justified mode, with I2SMCC_MRB.CRAMODE set to ‘0’, consecutive access to I2SMCC_THR writes first all the left channels enabled then all the right channels enabled. In I²S or Left-Justified mode, with I2SMCC_MRB.CRAMODE set to ‘1’, consecutive access to I2SMCC_THR writes first the left and right channels of the first I²S enabled, then the left and right channels of the second I²S enabled and continues in this manner until the last I²S enabled. In TDM or TDM Left-Justified mode, consecutive access to I2SMCC_THR writes the TDM channels enabled.

A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to I2SMCC_THR. In this case, the corresponding bit TXLUNFx or TXRUNFx in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit.

In case of transmit underrun, if the value of I2SMCC_MRA.TXSAME is ‘0’, then a ‘0’ is transmitted. If the value of I2SMCC_MRA.TXSAME is ‘1’, then the previous data word for the current transmit channel number is transmitted.

After a transmit underrun, the data written in I2SMCC_THR is discarded to keep the left and right channels synchronized.

Data words are right-justified in the common registers (I2SMCC_RHR and I2SMCC_THR). For the 16-bit compact stereo data format, the left sample uses bits [15:0] and the right sample uses bits [31:16] of the same data word. For the 8-bit compact stereo data format, the left sample uses bits [7:0] and the right sample uses bits [15:8] of the same data word.