8.1.2 AXI Subsystem

The AXI subsystem is comprised of:

  • CSS — CPU System and Security matrix
  • CHS — CPU High Speed matrix
  • APS — APB Client matrix
  • AXM — AXI Hosts matrix
  • ISS — Image Subsystem

AXI matrixes are based on NIC-400 r1p1 (by Arm Ltd.) and no settings are controlled by software. The respective hardware configurations used are described in the following sections. The default software configuration has been intensively tested and leads to best results in any conditions.

For complete details on the NIC-400 design, see the Arm specification on http://infocenter.arm.com/help/topic/com.arm.doc.ddi0475h/index.html

The device embeds Quality of Service management provided by Arm QoS-400 supplement to NIC-400. QoS-400 r1p1 is controlled by software. The respective hardware configurations used are described in the following sections. The default software configuration has been intensively tested and leads to best results in any conditions.

For complete details on the QoS-400, see the Arm specification on http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dsu0026g/index.html

This AXI subsystem (NICGPV) is connected to peripherals and to an AHB matrix (MATRIX) described below.

The following tables summarize the AXI matrix hosts and clients.

Table 8-2. AXI Hosts
Host Port Port Name
DDRC_P0 CHS AMIB0
Bridge to HSS M0 CHS AMIB1
ROM/OTP CSS AMIB2
CPKCC CSS AMIB3
APB0 CSS AMIB4
DDRC_P2 APS AMIB5
Bridge to HSS M1 APS AMIB6
APB1 APS AMIB7
APB2 APS AMIB8
APB3 APS AMIB9
APB4 APS AMIB10
APB7 APS AMIB11
DDR_P4 AXM AMIB12
Bridge to HSS M2 AXM AMIB13
CSI2DC AXM AMIB14
Table 8-3. AXI Clients
Client Port Port Name
CPU CHS ASIB0
OTP CSS ASIB1
XDMAC0 APS ASIB2
XDMAC1 APS ASIB3
DEBUG APS ASIB4
GMAC0 AXM ASIB5
GMAC1 AXM ASIB6
SDMMC0 AXM ASIB7
SDMMC1 AXM ASIB8
SDMMC2 AXM ASIB9
XDMAC2 AXM ASIB10