56.5.2 TDES Mode Register

This register can only be written if the WPEN bit is cleared in the TDES Write Protection Mode Register.

Name: TDES_MR
Offset: 0x04
Reset: 0x00000002
Property: Read/Write

Bit 3130292827262524 
 TAMPCLR        
Access R/W 
Reset 0 
Bit 2322212019181716 
       CFBS[1:0] 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
 LOD OPMOD[1:0]  SMOD[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 PKRSPKWO KEYMOD TDESMOD[1:0]CIPHER 
Access R/WR/WR/WR/WR/WR/W 
Reset 000010 

Bit 31 – TAMPCLR Tamper Pin Clear Key Enable

ValueDescription
0 A tamper detection event has no effect on TDES_KEYxWRy.
1 A tamper detection event immediately clears TDES_KEYxWRy.

Bits 17:16 – CFBS[1:0] Cipher Feedback Data Size

ValueNameDescription
0 SIZE_64BIT 64 bits
1 SIZE_32BIT 32 bits
2 SIZE_16BIT 16 bits
3 SIZE_8BIT 8 bits

Bit 15 – LOD Last Output Data Mode

Warning: In DMA mode, reading to TDES_ODATARx before the last data encryption/decryption process may lead to unpredictable result.
ValueDescription
0

No effect.

After each end of encryption/decryption, the output data is available either on TDES_ODATARx (Manual and Auto modes) .

In Manual and Auto modes, the DATRDY flag is cleared when at least one of the TDES_ODATARx is read.

1

The DATRDY flag is cleared when at least one of the Input Data Registers is written.

No further TDES_ODATARx reads are necessary between consecutive encryptions/decryptions (see Last Output Data Mode).

Bits 13:12 – OPMOD[1:0] Operating Mode

For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1.

ValueNameDescription
0 ECB Electronic Code Book mode
1 CBC Cipher Block Chaining mode
2 OFB Output Feedback mode
3 CFB Cipher Feedback mode

Bits 9:8 – SMOD[1:0] Start Mode

If a DMA transfer is used, 0x2 must be configured. See DMA Mode for more details.

ValueNameDescription
0 MANUAL_START Manual mode
1 AUTO_START Auto mode
2 IDATAR0_START TDES_IDATAR0 accesses only Auto mode

Bit 7 – PKRS Private Key Internal Register Select

ValueDescription
0 The keys used by the TDES are in the TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx registers.
1 The keys used by the TDES are the in the Private Key internal registers written through the Private Key bus.

Bit 6 – PKWO Private Key Write Once

Once PKWO is set to ‘1’, only a hardware reset sets this bit to ‘0’ internally. Writing it to ‘0’ with a register access has no impact (although the field will be read to value ‘0’).
ValueDescription
0 The Private Key internal register can be written multiple times through the Private Key bus.
1 The Private Key internal register can be written only once through the Private Key bus until hardware reset.

Bit 4 – KEYMOD Key Mode

ValueDescription
0

Three-key algorithm is selected.

1

Two-key algorithm is selected. There is no need to write TDES_KEY3WRy (or Private Pey internal registers with more than 128 bits).

Bits 2:1 – TDESMOD[1:0] ALGORITHM Mode

Values which are not listed in the table must be considered as “reserved”.

ValueNameDescription
0 SINGLE_DES

Single DES processing using TDES_KEY1WRy.

1 TRIPLE_DES

Triple DES processing using TDES_KEY1WRy, TDES_KEY2WRy and TDES_KEY3WRy .

2 XTEA XTEA processing using TDES_KEY1WRy and TDES_KEY2WRy.

Bit 0 – CIPHER Processing Mode

ValueNameDescription
0 DECRYPT Decrypts data.
1 ENCRYPT Encrypts data.