36.7.17 Secure PIO Configuration Register


Bit	31	30	29	28	27	26	25	24
	TAMPEN	ICFS	PCFS			EVTSEL[2:0]
Access	R/W	R	R			R/W	R/W	R/W
Reset	0	0	0			0	0	0


Bit	23	22	21	20	19	18	17	16
							DRVSTR[1:0]
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8
	SCHMITT	OPD	IFSCEN	IFEN		PDEN	PUEN	DIR
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
						FUNC[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 31 – TAMPEN Tamper Enable

Defines the action to do in case of tamper event for the I/O lines of the I/O group x defined in the Secure PIO Mask Register.

0 (NO_FREEZE): No effect on the selected I/O lines.

1 (FREEZE): The selected I/O lines are automatically set in GPIO input with pull-up in case of a tamper event detection.

Bit 30 – ICFS Interrupt Configuration Freeze Status

Gives information about the freeze state of the following fields of the read I/O line configuration:

• IFEN: Input Filter Enable

• IFSCEN: Input Filter Slow Clock Enable

• EVTSEL: Event Selection

0 (NOT_FROZEN): The fields are not frozen and can be written for this I/O line.

1 (FROZEN): The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.

Bit 29 – PCFS Physical Configuration Freeze Status

Gives information about the freeze state of the following fields of the read I/O line configuration:

• FUNC: I/O Line Function

• DIR: Direction

• PUEN: Pull-Up Enable

• PDEN: Pull-Down Enable

• OPD: Open-Drain

• SCHMITT: Schmitt Trigger

• DRVSTR: Drive Strength

0 (NOT_FROZEN): The fields are not frozen and can be written for this I/O line.

1 (FROZEN): The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.

Bits 26:24 – EVTSEL[2:0] Event Selection

Defines the type of event to detect on the I/O lines of the I/O group x according to the Secure PIO Mask Register.

Value	Name	Description
0	FALLING	Event detection on input falling edge
1	RISING	Event detection on input rising edge
2	BOTH	Event detection on input both edge
3	LOW	Event detection on low level input
4	HIGH	Event detection on high level input
5	–	Reserved
6	–	Reserved
7	–	Reserved

Bits 17:16 – DRVSTR[1:0] Drive Strength

Defines the drive strength of the I/O lines of the I/O group x according to the PIO Mask Register.

Value	Name	Description
0	LOW_OR_HS100	Low drive strength when the IO is driven in GPIO mode or by any non high-speed peripheral, else lowest drive for high-speed peripherals. Refer to the section “Electrical Characteristics” for values.
1	HIGH_OR_HS33	High drive strength when the IO is driven in GPIO mode or by any non high-speed peripheral, else highest drive for high-speed peripherals. Refer to the section “Electrical Characteristics” for values.
2	LOW_OR_HS66	Low drive strength when the IO is driven in GPIO mode or by any non high-speed peripheral, else middle-low drive for high-speed peripherals. Refer to the section “Electrical Characteristics” for values.
3	LOW_OR_HS50	Low drive strength when the IO is driven in GPIO mode or by any non high-speed peripheral, else middle-high drive for high-speed peripherals. Refer to the section “Electrical Characteristics” for values.

Bit 15 – SCHMITT Schmitt Trigger

Defines the Schmitt trigger configuration of the I/O lines of the I/O group x according to the Secure PIO Mask Register.

0 (ENABLED): Schmitt trigger is enabled for the selected I/O lines.

1 (DISABLED): Schmitt trigger is disabled for the selected I/O lines.

Bit 14 – OPD Open Drain

Defines the open drain configuration of the I/O lines of the I/O group x according to the Secure PIO Mask Register.

0 (DISABLED): The open drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.

1 (ENABLED): The open drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.

Bit 13 – IFSCEN Input Filter Slow Clock Enable

Defines the clock source of the glitch filtering for the I/O lines of the I/O group x according to the Secure PIO Mask Register.

Value	Description
0	The glitch filter is able to filter glitches with a duration less than 1 peripheral clock cycle for the selected I/O lines.
1	The debouncing filter is able to filter pulses with a duration less than 1 divided slow clock cycle for the selected I/O lines.

Bit 12 – IFEN Input Filter Enable

Defines if the glitch filtering is used for the I/O lines of the I/O group x according to the Secure PIO Mask Register.

0 (DISABLED): The input filter is disabled for the selected I/O lines.

1 (ENABLED): The input filter is enabled for the selected I/O lines.

Bit 10 – PDEN Pull-Down Enable

Defines the pull-down configuration of the I/O lines of the I/O group x according to the Secure PIO Mask Register.

PDEN can be written to 1 only if PUEN is written to 0.

0 (DISABLED): Pull-down is disabled for the selected I/O lines.

1 (ENABLED): Pull-down is enabled for the selected I/O lines only if PUEN is 0.

Bit 9 – PUEN Pull-Up Enable

Defines the pull-up configuration of the I/O lines of the I/O group x according to the Secure PIO Mask Register.

0 (DISABLED): Pull-up is disabled for the selected I/O lines.

1 (ENABLED): Pull-up is enabled for the selected I/O lines.

Bit 8 – DIR Direction

Defines the direction of the I/O lines of the I/O group x according to the Secure PIO Mask Register.

0 (INPUT): The selected I/O lines are pure inputs.

1 (OUTPUT): The selected I/O lines are enabled in output.

Bits 2:0 – FUNC[2:0] I/O Line Function

Defines the function for I/O lines of the I/O group x according to the Secure PIO Mask Register.

Value	Name	Description
0	GPIO	Selects the PIO mode for the selected I/O lines.
1	PERIPH_A	Selects peripheral A for the selected I/O lines.
2	PERIPH_B	Selects peripheral B for the selected I/O lines.
3	PERIPH_C	Selects peripheral C for the selected I/O lines.
4	PERIPH_D	Selects peripheral D for the selected I/O lines.
5	PERIPH_E	Selects peripheral E for the selected I/O lines.
6	PERIPH_F	Selects peripheral F for the selected I/O lines.
7	PERIPH_G	Selects peripheral G for the selected I/O lines.

Name:	S_PIO_CFGRx
Offset:	0x1004 + x*0x40 [x=0..4]
Reset:	0x00000000
Property:	Read/Write