36.7.12 PIO I/O Freeze Configuration Register

Writing this register will only affect I/O lines enabled in the PIO_MSKRx.

Name: PIO_IOFRx
Offset: 0x3C + x*0x40 [x=0..4]
Reset: 
Property: Write-only

Bit 3130292827262524 
 FRZKEY[23:16] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 FRZKEY[15:8] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 FRZKEY[7:0] 
Access WWWWWWWW 
Reset  
Bit 76543210 
       FINTFPHY 
Access WW 
Reset  

Bits 31:8 – FRZKEY[23:0] Freeze Key

ValueNameDescription
0x494F46 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.

Bit 1 – FINT Freeze Interrupt Configuration

Only a hardware reset can reset the FINT bit.
ValueDescription
0

No effect.

1

Freezes the following configuration fields of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46 (“IOF” in ASCII):

  • IFEN: Input Filter Enable
  • IFSCEN: Input Filter Slow Clock Enable
  • EVTSEL: Event Selection

Bit 0 – FPHY Freeze Physical Configuration

Only a hardware reset can reset the FPHY bit.
ValueDescription
0

No effect.

1

Freezes the following configuration fields of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46 (“IOF” in ASCII):

  • FUNC: I/O Line Function
  • DIR: Direction
  • PUEN: Pull-Up Enable
  • PDEN: Pull-Down Enable
  • OPD: Open-Drain
  • SCHMITT: Schmitt Trigger
  • DRVSTR: Drive Strength