8.3.7 UDDRC

The five ports are configured with PCFGQOS0_[port number], PCFGQOS1_[port number], PCFGWQOS0_[port number], PCFGWQOS1_[port number].

The following table summarizes how to program Outstanding Capability in each applicable section.

Table 8-7. Outstanding Capability Programming
Instance AXI Outstanding Management
DMA0 XDMAC0_GCFG.WRHP, XDMAC0_GCFG.WRMP, XDMAC0_GCFG.WRLP, XDMAC0_GCFG.RDHP, XDMAC0_GCFG.RDMP, XDMAC0_GCFG.RDSP
DMA1 XDMAC1_GCFG.WRHP, XDMAC1_GCFG.WRMP, XDMAC1_GCFG.WRLP, XDMAC1_GCFG.RDHP, XDMAC1_GCFG.RDMP, XDMAC1_GCFG.RDSP
DMA2 XDMAC2_GCFG.WRHP, XDMAC2_GCFG.WRMP, XDMAC2_GCFG.WRLP, XDMAC2_GCFG.RDHP, XDMAC2_GCFG.RDMP, XDMAC2_GCFG.RDSP
GMAC0 GMAC0_AMP register
GMAC1 GMAC1_AMP register

The following table summarizes how to program QoS in each applicable section.

Table 8-8. Quality of Service Programming
Instance QoS Management

Default Value

Transaction Outstanding Latency Regulation in NICGPV
CPU ASIB[0] in NICGPV(1) 0 –
DMA0, per channel QoS in XDMAC0_CNDC[channel number] registers 0 –
DMA1, per channel QoS in XDMAC1_CNDC[channel number] registers 0 –
DMA2, per channel QoS in XDMAC2_CNDC[channel number] registers 0 X
GMAC0 ASIB[5] in NICGPV 0 X
GMAC1 ASIB[6] in NICGPV 0 X
SDMMC0 Peripheral for descriptors, in SDMMC0_ACR register 0 X
SDMMC1 Peripheral for descriptors, in SDMMC1_ACR register 0 X
SDMMC2 Peripheral for descriptors, in SDMMC2_ACR register 0 X
ISC Peripheral in ISC_DCFG register 0 –
AHB matrix port 3 SFR_HSS_AXIQOS Register 0 –
DDR port, per port UDDRC in PCFGQOS0_[port number], PCFGQOS1_[port number], PCFGWQOS0_[port number], PCFGWQOS1_[port number] registers 0 –
AHB matrix hosts (including CPU)

MATRIX_PRAS[port number]

MATRIX_PRBS[port number]

0

2

 –
Note:
  1. This QoS is not propagated to the AHB matrix through the M0 port.

For details, refer to the relevant peripheral sections and to the sections NIC-400 Global Programmer’s View (NICGPV), Bus Matrix (MATRIX) and Special Function Registers (SFR).