48.6.4.1 Direct Mapping Registers
The registers SPDIFTX_CHySx and SPDIFTX_CHyUDx configure the 192-bit Channel Status and User Data for each channel.
In order to use these registers to configure the 192-bit Channel Status and User Data for each channel, the following settings must be respected:
- SPDIFTX_MR.CMODE must be lower than ‘3’.
- SPDIFTX_EMR.CSM must not be set to ‘1’.
- SPDIFTX_EMR.UDM must not be set to ‘1’.
The SPDIFTX_CHySx and SPDIFTX_CHyUDx registers must be configured before enabling the SPDIFTX. Then, if the Channel Status or User Data value must be changed for each new 192-frame block, SPDIFTX_ISR.CSRDY and SPDIFTX_ISR.UDRDY flags indicate when the value of the CHySx and CHyUDx can be changed.
Note: The registers must be written
consecutively to ensure the data is ready for the next block.