16.10.5 External Bus Clock

The SMC provides an external bus clock synchronous to the address, data and control signals. When SMC_CFGCLK.CLKEN=1, the frequency of the output clock is periph_clock/ (CLKDIV+1).

The start of the access to the external memory device can be aligned on the rising or falling edge of the output clock by configuring the SMC_CFGCLK.CLKEDGE.