54.5.21 AES Write Protection Mode Register
| Name: | AES_WPMR |
| Offset: | 0xE4 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ACTION[2:0] | FIRSTE | WPCREN | WPITEN | WPEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 31:8 – WPKEY[23:0] Write Protection Key
| Value | Name | Description |
|---|---|---|
| 0x414553 | PASSWD |
Writing any other value in this field aborts the write operation of the WPEN,WPITEN,WPCREN bits. Always reads as 0. |
Bits 7:5 – ACTION[2:0] Action on Abnormal Event Detection
When the field AES_WPMR.ACTION differs from 0 and an abnormal event or internal state is detected, the AES is locked until the unlock command is issued (AES_CR.UNLOCK=1). The lock source must be cleared before performing the unlock command. If AES_WPSR.SEQE=1, the following two actions must be performed:
1/ Read AES_WPSR.
2/ Issue software reset by writing a 1 in AES_CR.SWRST.
A specific configuration applies where the sequence does not clear the lock source (AES_WPSR=0).
If AES_WPSR.SEQE remains high after the clearing sequence, then only a hardware reset will unlock the AES. A hardware reset can be performed by issuing a reset controller software reset (refer to the section “Reset Controller (RSTC)”). This condition can be met when AES_EMR.PKWL=1 and a key has been loaded through the Private Key bus. The key loaded through the key bus is corrupted, but it is impossible to reload a new key unless a hardware reset is issued.
| Value | Name | Description |
|---|---|---|
| 0 | REPORT_ONLY | No action (stop or clear key) is performed when one of PKRPVS, WPVS, CGD, SEQE, or SWE flags is set. |
| 1 | LOCK_PKRPVS_WPVS_SWE | If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. |
| 2 | LOCK_CGD_SEQE | If a processing is in progress when the AES_WPSR.CGD/SEQE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. |
| 3 | LOCK_ANY_EV | If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. |
| 4 | CLEAR_PKRPVS_WPVS_SWE | If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared. |
| 5 | CLEAR_CGD_SEQE | If a processing is in progress when the AES_WPSR.CGD/SEQE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared. |
| 6 | CLEAR_ANY_EV | If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared. |
Bit 4 – FIRSTE First Error Report Enable
| Value | Description |
|---|---|
| 0 | The last write protection violation source is reported in AES_WPSR.WPVSRC and the last software control error type is reported in AES_WPSR.SWETYP. The AES_ISR.SECE flag is set at the first error occurrence within a series. |
| 1 | Only the first write protection violation source is reported in AES_WPSR.WPVSRC and only the first software control error type is reported in AES_WPSR.SWETYP. The AES_ISR.SECE flag is set at the first error occurrence within a series. |
Bit 2 – WPCREN Write Protection Control Enable
| Value | Description |
|---|---|
| 0 |
Disables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII). |
| 1 |
Enables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII). |
Bit 1 – WPITEN Write Protection Interruption Enable
| Value | Description |
|---|---|
| 0 |
Disables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII). |
| 1 |
Enables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII). |
Bit 0 – WPEN Write Protection Configuration Enable
See Register Write Protection for the list of registers that can be write-protected.
| Value | Description |
|---|---|
| 0 |
Disables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII). |
| 1 |
Enables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII). |