54.5.17 AES Extended Mode Register

This register can only be written if the WPEN bit is cleared in the AES Write Protection Mode Register.

Name: AES_EMR
Offset: 0xB0
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 BPE        
Access R/W 
Reset 0 
Bit 2322212019181716 
 NHEAD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PADLEN[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PKRSPKWLPLIPDPLIPEN  APMAPEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 31 – BPE Block Processing End

ValueDescription
0

AES_ISR.DATRDY flag reports only the end message encryption processing. No intermediate block processing is reported when SMOD=2. When a DMA is used to transfer data, BPE must be cleared.

1

AES_ISR.DATRDY flag reports each end of block processing when SMOD=2. When AES_IDATARx are not loaded by a DMA and SMOD=2, this bit can be written to 1 to rise the AES_ISR.DATRDY flag when a new data block can be written.

Bits 23:16 – NHEAD[7:0] IPSec Next Header

ValueDescription
0–255

IPSec Next Header field

Bits 15:8 – PADLEN[7:0] Auto Padding Length

ValueDescription
0–255

Padding length in bytes

Bit 7 – PKRS Private Key Internal Register Select

ValueDescription
0

The key used by the AES is in the AES_KEYWRx registers.

1

The key used by the AES is in the Private Key internal registers written through the Private Key bus.

Bit 6 – PKWL Private Key Write Lock

Once PKWL is set to ‘1’, only a hardware reset sets this bit to ‘0’ internally. Writing it to '0' with a register access has no impact (although the field will be read to value ‘0’).
ValueDescription
0

The Private Key internal registers can be written multiple times via the Private Key bus.

1

The Private Key internal registers can be written only once via the Private Key bus until hardware reset.

Bit 5 – PLIPD Protocol Layer Improved Performance Decipher

ValueDescription
0

Protocol layer improved performance is in ciphering mode.

1

Protocol layer improved performance is in deciphering mode.

Bit 4 – PLIPEN Protocol Layer Improved Performance Enable

ValueDescription
0

Protocol layer improved performance is disabled.

1

Protocol layer improved performance is enabled.

Bit 1 – APM Auto Padding Mode

ValueDescription
0

Auto Padding performed according to IPSec standard.

1

Auto Padding performed according to SSL standard.

Bit 0 – APEN Auto Padding Enable

ValueDescription
0

Auto Padding feature is disabled.

1

Auto Padding feature is enabled.