10.7.1 EIC Glitch Filter Configuration Status Register
| Name: | EIC_GFCS |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDY1 | RDY0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bits 0, 1 – RDYx Filter x Configuration Ready
| Value | Description |
|---|---|
| 0 | The interrupt line x glitch filter is not yet ready for use due to a previous write to EIC_SCFGxR, or the glitch filter is not implemented for this interrupt line. The glitch filter must not be reprogrammed in EIC_SCFGxR. |
| 1 | The interrupt line x glitch filter configuration is done and the glitch filter is active. The glitch filter can be programmed in EIC_SCFGxR. |