10.7.2 EIC Source Configuration Register x
This register can only be written if WPCFEN is cleared in the EIC Write Protection Mode register.
| Name: | EIC_SCFGxR |
| Offset: | 0x04 + x*0x04 [x=0..1] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FRZ | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LVL | POL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GFEN | GFSEL[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 31 – FRZ Interrupt Line Freeze
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
EIC_SCFGxR is frozen until hardware reset. |
Bit 16 – EN Source Enable
| Value | Description |
|---|---|
| 0 |
The EIC source x is disabled. Any source edge or level detection is discarded. |
| 1 |
The EIC source x is enabled. |
Bit 9 – LVL Level Detection
| Value | Description |
|---|---|
| 0 |
The EIC source x interrupt status is set on a valid source edge. |
| 1 |
The EIC source x interrupt status is set on a valid source level. |
Bit 8 – POL Polarity
| Value | Description |
|---|---|
| 0 |
The EIC source x is active low if LVL is set, or active on falling edge if LVL is cleared. |
| 1 |
The EIC source x is active high if LVL is set, or active on rising edge if LVL is cleared. |
Bit 4 – GFEN Glitch Filter Enable
| Value | Description |
|---|---|
| 0 | The glitch filter is disabled or not implemented for EIC source x. Any source x change is forwarded as is to the source detection logic. |
| 1 | The glitch filter is enabled for EIC source x. The EIC source x glitches are filtered according to Interrupt Line Characteristics. |