70.6.2.3 USB-Type C Port Controller Status Register Management

The TCPC software regularly polls TCPC_UPS to meet the Universal Serial Bus Type-C™ Port Controller Interface Specification CC debouncing requirements, in particular after V_BUS detection or driving.

TCPC_SSR and TCPC_CSR are then used for the software to change the state of the CC Status (TCPC_CCS), Power Status (TCPC_PS), Fault Status (TCPC_FS) and Alert (TCPC_AL) registers.

The TCPC Role Control (TCPC_RCTL), Fault Control (TCPC_FCTL) and Command (TCPC_CMD) registers are to be read by the software to control the USB-Type C hardware through TCPC_UPC and external controls such as V_BUS.

The bits in registers TCPC_CCS, TCPC_PS and TCPC_FS are set from the Set Status (TCPC_SSR) register.

The bits in registers TCPC_CCS and TCPC_PS are cleared from the Clear Status (TCPC_CSR) register.

TCPC_AL is set from the Set Alert (TCPC_SAR) register.

The bits in TCPC_FS and TCPC_AL are cleared by writing each bit in these registers to ‘1’. Refer to the Universal Serial Bus Type-C™ Port Controller Interface Specification (see Reference Documents).

Note that any unmasked change in TCPC_FS or TCPC_PS, or any change in TCPC_CCS also automatically sets, respectively, FLT, PWRS and CCS bits in TCPC_AL.

Setting an unmasked bit in TCPC_AL triggers the Alert interrupt to the Interrupt Controller to signal status changes to the TCPM software.

Refer to the Universal Serial Bus Type-C™ Port Controller Interface Specification and Universal Serial Bus Type-C Cable and Connector Specification (see Reference Documents) for a detailed description of the algorithms to be implemented to support the various USB Type-C features.