9.6.3 SDIO Client Interface Timing Diagram

The SDIO Client interface timing for ATWILC3000A is shown in the following figure.
Figure 9-3. SDIO Client Timing Diagram

The following table provides the SDIO Client timing parameters for the ATWILC3000A.

Table 9-10. SDIO Client Timing Parameters
ParameterSymbolMin.Max.Units
Clock Input Frequency(1)fPP—50MHz
Clock Low Pulse WidthtWL6—ns
Clock High Pulse WidthtWH7—
Clock Rise TimetLH05
Clock Fall TimetHL05
Input Setup TimetISU6—
Input Hold TimetIH8—
Output Delay(2)tODLY311
Note:
  1. Maximum clock frequency specified is limited by the SDIO Client interface internal design; actual maximum clock frequency can be lower and depends on the specific PCB layout.
  2. Timing based on 15 pF output loading.