9.6.1 I²C Client Interface Timing Diagram

The I²C Client timing diagram for the ATWILC3000A is shown in the following figure.

The following table provides the I²C Client timing parameters for the ATWILC3000A.

Table 9-8. I²C Client Timing Parameters
Parameter	Symbol	Min.	Max.	Units	Remarks
SCL Clock Frequency	f_SCL	0	400	kHz	—
SCL Low Pulse Width	t_WL	1.3	—	µs	—
SCL High Pulse Width	t_WH	0.6	—	µs	—
SCL, SDA Fall Time	t_HL	—	300	ns	—
SCL, SDA Rise Time	t_LH	—	300	ns	This is dictated by external components
Start Setup Time	t_SUSTA	0.6	—	µs	—
Start Hold Time	t_HDSTA	0.6	—	µs	—
SDA Setup Time	t_SUDAT	100	—	ns	—
SDA Hold Time	t_HDDAT	0	—	ns	Client and Host default
SDA Hold Time	t_HDDAT	40	—	µs	Host programming option
Stop Setup Time	t_SUSTO	0.6	—	µs	—
Bus Free Time between Stop and Start	t_BUF	1.3	—	µs	—
Glitch Pulse Reject	t_PR	0	50	ns	—

9.6.1 I2C Client Interface Timing Diagram