19.7.5 3.3V Brown-Out Detector (BOD33) Control

Name: BOD33
Offset: 0x10
Reset: Determined from NVM User Row
Property: Write-Synchronized Bit(s), PAC Write-Protection

Bit 3130292827262524 
 VBATLEVEL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 LEVEL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00xxxxxx 
Bit 15141312111098 
  PSEL[2:0]HYST[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 000xxxx 
Bit 76543210 
 RUNBKUPRUNHIBRUNSTDBYSTDBYCFGACTION[1:0]ENABLE  
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000yyz 

Bits 31:24 – VBATLEVEL[7:0]  BOD33 Threshold Level on VBAT

This field sets the triggering voltage threshold for the BOD33 when the BOD33 monitors VBAT in battery backup sleep mode.

This field is not synchronized.

Bits 23:16 – LEVEL[7:0]  BOD33 Threshold Level on VDD

This field sets the triggering voltage threshold for the BOD33 when the BOD33 monitors VDD. If an hysteresis value is programmed (BOD33.HYST), this field corresponds to the lower threshold VBOD(min).

These bits are loaded from NVM User Row at start-up.

This field is not synchronized.

VBOD(min) = (1.5 + (SUPC.BOD33.LEVEL[7:0] * VBOD33LEVEL_STEP))

VBOD(max) = (VBOD(min) + (SUPC.BOD33.HYST[3:0] * VBOD33HYST_STEP))

If a hysteresis value is programmed, the following equation must be respected to avoid any overflow on VBOD(max) : LEVEL[7:0] value < 255 - HYST[3:0] value

Bits 14:12 – PSEL[2:0] Prescaler Select

Selects the prescaler divide-by output for the BOD33 sampling mode available in hibernate, backup or battery backup mode. The input clock comes from the OSCULP32K 32.768 kHz output.

ValueNameDescription
0x0 NODIV Not divided: Sampling mode is OFF.
0x1 DIV4 Divide clock by 4
0x2 DIV8 Divide clock by 8
0x3 DIV16 Divide clock by 16
0x4 DIV32 Divide clock by 32
0x5 DIV64 Divide clock by 64
0x6 DIV128 Divide clock by 128
0x7 DIV256 Divide clock by 256

Bits 11:8 – HYST[3:0]  BOD33 Hysteresis Voltage Value on VDD

This field sets the hysteresis voltage value related to "BOD33 Threshold Level on VDD" field when the BOD33 monitors VDD.

These bits are loaded from NVM User Row at start-up.

This field is not synchronized.

Note: The hysteresis feature is not functional while the device is in STANDBY sleep mode.
ValueDescription
0 No hysteresis.
N Hysteresis value is set to N*VBOD33HYST_STEP.

See the Electrical Characteristics section for the VBOD33HYST_STEP voltage level.

Bit 7 – RUNBKUP  BOD33 Configuration in Backup Sleep Mode

This field is not synchronized.

ValueDescription
0 In backup sleep mode, the BOD33 is disabled.
1 In backup sleep mode, the BOD33 is enabled and configured in sampling mode.

Bit 6 – RUNHIB  BOD33 Configuration in Hibernate Sleep Mode

This field is not synchronized.

ValueDescription
0 In hibernate sleep mode, the BOD33 is disabled.
1 In hibernate sleep mode, the BOD33 is enabled and configured in sampling mode.

Bit 5 – RUNSTDBY Run in Standby

This bit is not synchronized.

ValueDescription
0 In standby sleep mode, the BOD33 is disabled.
1 In standby sleep mode, the BOD33 is enabled.

Bit 4 – STDBYCFG  BOD33 Configuration in Standby Sleep Mode

If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BOD33 configuration in standby sleep mode.

This field is not synchronized.

ValueDescription
0 In standby sleep mode, the BOD33 is enabled and configured in normal mode.
1 In standby sleep mode, the BOD33 is enabled and configured in low power mode.

Bits 3:2 – ACTION[1:0]  BOD33 Action

These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold.

These bits are loaded from NVM User Row at start-up.

This field is not synchronized.

Value Name Description
0x0 NONE No action
0x1 RESET The BOD33 generates a reset
0x2 INT The BOD33 generates an interrupt
0x3 BKUP The BOD33 puts the device in battery backup sleep mode.

Bit 1 – ENABLE Enable

This bit is loaded from NVM User Row at start-up.

ValueDescription
0 BOD33 is disabled.
1 BOD33 is enabled.