42.6.3.1.1 Hall Sensor Control

On any update of the filter output:

  • The filter output value is checked to be a valid Hall value. If an invalid Hall code is reported, the Hall Error bit in the Status register will be set (STATUS.HERR).
  • The OVF Interrupt Flag bit is set (INTFLAG.OVF) if CC0[2:0] matches the filter output value, stored in LSB part of the COUNTER. An optional overflow interrupt or Event output is generated on the same condition detection.
  • The window counter is checked to be between the value of the MSB part of CC0 and CC1, and reset to 0 value. If an error is detected, the Window Error bit in the Status register (STATUS.WINERR) is set.
  • The delay counter is started, and MC0 optional interrupt or event is generated when the delay counter matches the MSB part of CC0.
  • Optional MC1 interrupt or event is generated when the delay counter matches the MSB part of CC1.

Any error condition will set the Error Interrupt Flag (INTFLAG.ERR). An optional interrupt or event output is generated on the same condition detection.

Figure 42-12. Hall Waveforms