37.6.1.1 Initialization

The I²S features two Clock Units, one Transmit Serializer, and One Receive Serializer. The Transmit Serializer uses Clock Unit 0, while the Receive Serializer can either share the same Clock Unit 0 or use the Clock Unit 1.

Before enabling the I²S, the following registers must be configured:

• Clock Control registers (CLKCTRLn)
• Serializer Control registers (TXCTRL and/or RXCTRL)

In Host mode, one of the generic clocks for the I²S must also be configured to operate at the required frequency, as described in 37.6.1 Principle of Operation.

• fs is the sampling frequency that defines the frame period
• CLKCTRLn.NBSLOTS defines the number of slots in each frame
• CLKCTRLn.SLOTSIZE defines the number of bits in each slot
• SCKn frequency must be f_SCKn = fs × number_of_slots × number_of_bits_per_slot)

Once the configuration has been written, the I²S Clock Units and Serializers can be enabled by writing a '1' to the CKENn, TXEN, and/or RXEN bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if Serializers are enabled.

The Clock Units, the Transmit Serializer and the Receive Serializer can be disabled independently by writing a '0' to CTRLA.CKENn, CTRLA.TXEN, and CTRLA.RXEN, respectively. Once requested to stop, they will only stop when the pending transmit frames will be completed, if any. When requested to stop, the ongoing reception of the current slot will be completed and then the Serializer will be stopped.