49.6.1 Configuration Register
| Name: | CFG |
| Offset: | 0x00 |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UALGO[2:0] | UIHASH | DUALBUFF | ASCD | ||||||
| Access | - | - | - | - | - | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BBC[3:0] | SLBDIS | EOMDIS | WBDIS | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 15:13 – UALGO[2:0] User SHA Algorithm
| Value | Name | Description |
|---|---|---|
| 0 | SHA1 |
SHA1 algorithm processed |
| 1 | SHA256 |
SHA256 algorithm processed |
| 4 | SHA224 |
SHA224 algorithm processed |
| Other | - | Reserved |
Bit 12 – UIHASH User Initial Hash Value
| Value | Description |
|---|---|
| 0 | The secure hash standard provides the initial hash value. |
| 1 | The initial hash value is programmable. Field UALGO provides the SHA algorithm. The ALGO field of the RCFGn structure member has no effect. |
Bit 9 – DUALBUFF Dual Input Buffer
| Value | Description |
|---|---|
| 0 | Dual Input buffer mode is disabled. |
| 1 | Dual Input buffer mode is enabled (Better performances, higher bandwidth required on system bus). |
Bit 8 – ASCD Automatic Switch To Compare Digest
| Value | Description |
|---|---|
| 0 | Automatic mode is disabled. |
| 1 | When this mode is enabled, the ICM controller automatically switches to active monitoring after the first Main List pass. Both CDWBN and WBDIS bits have no effect. A '1' must be written to the End of Monitoring bit in the Region Configuration register (RCFG.EOM) to terminate the monitoring. |
Bits 7:4 – BBC[3:0] Bus Burden Control
This field is used to control the burden of the ICM system bus. The number of system clock cycles between the end of the current processing and the next block transfer is set to 2BBC. Up to 32768 cycles can be inserted.
Bit 2 – SLBDIS Secondary List Branching Disable
| Value | Description |
|---|---|
| 0 | Branching to the Secondary List is permitted. |
| 1 | Branching to the Secondary List is forbidden. The NEXT field of the RNEXT structure member has no effect and is always considered as zero. |
Bit 1 – EOMDIS End of Monitoring Disable
| Value | Description |
|---|---|
| 0 | End of Monitoring is permitted. |
| 1 | End of Monitoring is forbidden. The EOM bit of the RCFG structure member has no effect. |
Bit 0 – WBDIS Write Back Disable
1:
When the Automatic Switch to Compare Digest bit of this register (CFG.ASCD) is written to '1', this bit value has no effect.
| Value | Description |
|---|---|
| 0 | Write Back Operations are permitted. |
| 1 | Write Back Operations are forbidden: Context register CDWBN bit is internally set to '1' and cannot be modified by a linked list element. The CDWBN bit of the RCFG structure member has no effect. |