49.6.5 Interrupt Disable Register
Name: | IDR |
Offset: | 0x14 |
Property: | Write-Only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
URAD | |||||||||
Access | W | ||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RSU[3:0] | REC[3:0] | ||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
RWC[3:0] | RBE[3:0] | ||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RDM[3:0] | RHC[3:0] | ||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit 24 – URAD Undefined Register Access Detection Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | Undefined Register Access Detection interrupt is disabled. |
Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When RSU[i] is written to '1', the region i Status Updated interrupt is disabled. |
Bits 19:16 – REC[3:0] Region End bit Condition detected Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When REC[i] is written to '1', the region i End bit Condition interrupt is disabled. |
Bits 15:12 – RWC[3:0] Region Wrap Condition Detected Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When RWC[i] is written to '1', the Region i Wrap Condition interrupt is disabled. |
Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When RBE[i] is written to '1', the Region i Bus Error interrupt is disabled. |
Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When RDM[i] is written to '1', the Region i Digest Mismatch interrupt is disabled. |
Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Disable
Value | Description |
---|---|
0 | No effect. |
1 | When RHC[i] is written to '1', the Region i Hash Completed interrupt is disabled. |