49.6.7 Interrupt Status Register

Name: ISR
Offset: 0x1C
Reset: 0x0
Property: Read-Only

Bit 3130292827262524 
        URAD 
Access R 
Reset 0 
Bit 2322212019181716 
 RSU[3:0]REC[3:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RWC[3:0]RBE[3:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RDM[3:0]RHC[3:0] 
Access RRRRRRRR 
Reset 00000000 

Bit 24 – URAD Undefined Register Access Detection Status

The URAD bit is only reset by the SWRST bit in the CTRL register.

The Undefined Register Access Trace bit field in the Undefined Access Status Register (UASR.URAT) indicates the unspecified access type.

ValueDescription
0 No undefined register access has been detected since the last SWRST.
1 At least one undefined register access has been detected since the last SWRST.

Bits 23:20 – RSU[3:0] Region Status Updated Detected

RSU[i] is set when a region status updated condition is detected.

Bits 19:16 – REC[3:0] Region End bit Condition Detected

REC[i] is set when an end bit condition is detected.

Bits 15:12 – RWC[3:0] Region Wrap Condition Detected

RWC[i] is set when a wrap condition is detected.

Bits 11:8 – RBE[3:0] Region Bus Error

RBE[i] is set when a bus error is detected while hashing memory region i.

Bits 7:4 – RDM[3:0] Region Digest Mismatch

RDM[i] is set when there is a digest comparison mismatch between the hash value of region i and the reference value located in the Hash Area.

Bits 3:0 – RHC[3:0] Region Hash Completed

RHC[i] is set when the ICM has completed the region with identifier i.