35.6.8.5 Instruction Frame Transmission Examples

All waveforms in the following examples describe SPI transfers in SPI Clock mode 0 (BAUD.CPOL=0 and BAUD.CPHA=0). All system bus accesses described below refer to the system bus address phase. System bus wait cycles and system bus data phases are not shown.

Example 1

Instruction in Single-bit SPI, without address, without option, without data.

Command: CHIP ERASE (C7h).

  • Write 0x0000_00C7 to INSTRCTRL register.
  • Write 0x0000_0010 to INSTRFRAME register.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-12. Instruction Transmission Waveform 1

Example 2

Instruction in Quad SPI, without address, without option, without data.

Command: POWER DOWN (B9h)

  • Write 0x0000_00B9 to INSTRCTRL register.
  • Write 0x0000_0016 to INSTRFRAME register.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-13. Instruction Transmission Waveform 2

Example 3

Instruction in Single-bit SPI, with address in Single-bit SPI, without option, without data.

Command: BLOCK ERASE (20h)

  • Write the address (of the block to erase) to QSPI_AR.
  • Write 0x0000_0020 to INSTRCTRL register.
  • Write 0x0000_0030 toINSTRFRAME register.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-14. Instruction Transmission Waveform 3

Example 4

Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI.

Command: SET BURST (77h)

  • Write 0x0000_0077 to INSTRCTRL register.
  • Write 0x0000_2090 to INSTRFRAME register.
  • Read INSTRFRAME register (dummy read) to synchronize system bus accesses.
  • Write data to the system bus memory space (0x0400_0000–0x0500_0000). The address of the system bus write accesses is not used.
  • Write the LASTXFR bit in CTRLA register to '1'.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-15. Instruction Transmission Waveform 4

Example 5

Instruction in Single-bit SPI, with address in Dual SPI, without option, with data write in Dual SPI.

Command: BYTE/PAGE PROGRAM (02h)

  • Write 0x0000_0002 to INSTRCTRL register.
  • Write 0x0000_30B3 to INSTRFRAME register.
  • Read INSTRFRAME register (dummy read) to synchronize system bus accesses.

  • Write data to the QSPI system bus memory space (0x040 00000–0x0500_0000).

    The address of the first system bus write access is sent in the instruction frame.

    The address of the next system bus write accesses is not used.

  • Write LASTXFR bit in CTRLA register to '1'.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-16. Instruction Transmission Waveform 5

Example 6

Instruction in Single-bit SPI, with address in Single-bit SPI, without option, with data read in Quad SPI, with eight dummy cycles.

Command: QUAD_OUTPUT READ ARRAY (6Bh)

  • Write 0x0000_006B to INSTRCTRL register.
  • Write 0x0008_10B2 ti INSTRFRAME register.
  • Read QSPI_IR (dummy read) to synchronize system bus accesses.

  • Read data from the QSPI system bus memory space (0x040 00000–0x0500_0000).

    The address of the first system bus read access is sent in the instruction frame.

    The address of the next system bus read accesses is not used.

  • Write the LASTXFR bit in CTRLA register to '1'.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-17. Instruction Transmission Waveform 6

Example 7

Instruction in Single-bit SPI, with address and option in Quad SPI, with data read from Quad SPI, with four dummy cycles, with fetch and continuous read.

Command: FAST READ QUAD I/O (EBh) - 8-BIT OPTION (0x30h)

  • Write 0x0030_00EB to INSTRCTRL register.
  • Write 0x0004_33F4 to INSTRFRAME register.
  • Read INSTRFRAME register (dummy read) to synchronize system bus accesses.

  • Read data from the QSPI system bus memory space (0x040 00000–0x0500_0000).

    Fetch is enabled, the address of the system bus read accesses is always used.

  • Write LASTXFR bit in CTRLA register to '1'.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-18. Instruction Transmission Waveform 7

Example 8

Instruction in Quad SPI, with address in Quad SPI, without option, with data read from Quad SPI, with two dummy cycles, with fetch.

Command: HIGH-SPEED READ (0Bh)

  • Write 0x0000_000B to INSTRCTRL register.
  • Write 0x0002_20B6 to INSTRFRAME register.
  • Read INSTRFRAME register (dummy read) to synchronize system bus accesses.

  • Read data in the QSPI system bus memory space (0x040 00000–0x0500_0000).

    Fetch is enabled, the address of the system bus read accesses is always used.

  • Write LASTXFR bit in CTRLA register to '1'.
  • Wait for INTFLAG.INSTREND to rise.
Figure 35-19. Instruction Transmission Waveform 8