18.6.4.2 Additional Features

Dealing with Delay in the DFLL in Closed-Loop Mode

The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRLB.CCDIS) in the DFLL Control register. Enabling chill cycles might double the lock time.

Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRLB.QLDIS) in the DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same.

Note: During a maximum 30 cycles of the reference clock period, between lock flag asserted and frequency stabilization, DFLL accuracy will be limited. To minimize the cycle-to-cycle jitter during lock search, in addition to selecting a low step value (DFLLMUL.FSTEP, DFLLMUL.CSTEP), it is recommended to disable the Quick Lock feature.

USB Clock Recovery Mode

USB Clock Recovery mode can be used to create the 48 MHz USB clock from the USB Start Of Frame (SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit in the DFLL Control register (DFLLCTRLB.USBCRM and DFLLCTRLB.MODE).

Note: The DFLLCTRLB.USBCRM register must not be set if the USB is disabled.

Changing the reference clock source (CLK_DFLL_REF) must be done as follows:

  • Disable USB
  • Switch the DFLL48M in open loop mode
  • Change the reference clock (DFLLCTRLB.USBCRM)
  • Switch the DFLL48M in close loop mode
  • Enable USB
Note: When USB Clock Recovery mode is enabled, the GCLK DFLL48M reference clock (GCLK_DFLL48M_REF) must be disabled.

In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the USB bus activity, and have no valid meaning. The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRLB.BPLCKC bit state is ignored, and the value stored in the DFLLVAL.COARSE will be used as final Coarse value.

The COARSE value for a calibrated 48 MHz frequency is loaded from NVM after any system reset and may vary in operating modes different of the USB Clock Recovery Mode. The initial COARSE value can be saved and restored by the software if necessary.

The locking procedure will also go instantaneously to the fine lock search.

The DFLLCTRLB.QLDIS bit must be cleared and DFLLCTRLB.CCDIS should be set to speed up the lock phase. The DFLLCTRLB.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.

Wake from Sleep Modes

DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit (DFLLCTRLB.LLAW) in the DFLL Control register.

If DFLLCTRLB.LLAW is zero, the DFLL48M will be re-enabled and start running with the same configuration as before being disabled, even if the reference clock is not available. The locks will not be lost. Thus it is important that the user checks that the DFLL48M has reached the COARSE and FINE lock stage before entering a sleep mode. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift during sleep if DFLLCTRLB.STABLE is zero.

If DFLLCTRLB.LLAW is one when disabling the DFLL48M, the DFLL48M will lose all its locks, and needs to regain these through the full lock sequence.

Note: When reconfiguring the DFLL, wait for the lock status to set to ‘0’ (STATUS.DFLLLOCK = 0) after disabling the DFLL (DFLLCTRLA.ENABLE = 0).

The DFLLCTRLB.LLAW bit update must be done as follows:

  1. Disable the DFLL (DFLLCTRLA.ENABLE = 0).
  2. Wait for synchronization (DFLLSYNC.ENABLE = 0).
  3. Wait for STATUS.DFLLRDY = 0.
  4. Update the DFLLCTRLB.LLAW bit.

Wait for Lock

DFLL48M can optionally control the issued clock. This is configured by the Wait For Lock bit (DFLLCTRLB.WAITLOCK) in the DFLL Control register. If DFLLCTRLB.WAITLOCK is zero, the DFLL48M will issue a clock immediately after the ready bit (STATUS.DFLLRDY) has risen. If DFLLCTRLB.WAITLOCK is one, the DFLL48M will issue a clock immediately after the fine lock bit (STATUS.DFLLCKF) has risen. Using the wait for lock feature allows a better accuracy of the issued DFLL48M clock, conversely it increases the startup time of the DFLL48M clock.

Accuracy

There are two main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy when fine lock is achieved.

  • Fine resolution: The frequency step between two Fine values.
  • The accuracy of the reference clock.