39.7.6 Reception Holding Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | RHR |
Offset: | 0x14 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
RDATA[31:24] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RDATA[23:16] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
RDATA[15:8] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RDATA[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:0 – RDATA[31:0] Reception Data
ISIZE | SCALE | DSIZE | Description |
---|---|---|---|
8_BITS | - | 1_DATA | RDATA[7:0] is useful |
2_DATA | RDATA[15:0] is useful | ||
4_DATA | RDATA[31:0] is useful | ||
10_BITS | 0 (OFF) | 1_DATA | RDATA[9:0] is useful |
2_DATA | RDATA[9:0] and RDATA[25:16] are useful | ||
1 (ON) | 1_DATA | RDATA[15:0] is useful | |
2_DATA | RDATA[31:0] is useful | ||
12_BITS | 0 (OFF) | 1_DATA | RDATA[11:0] is useful |
2_DATA | RDATA[11:0] and RDATA[27:16] are useful | ||
1 (ON) | 1_DATA | RDATA[15:0] is useful | |
2_DATA | RDATA[31:0] is useful | ||
14_BITS | 0 (OFF) | 1_DATA | RDATA[13:0] is useful |
2_DATA | RDATA[13:0] and RDATA[29:16] are useful | ||
1 (ON) | 1_DATA | RDATA[15:0] is useful | |
2_DATA | RDATA[31:0] is useful |