11.8 Power On Considerations

The Power On procedure starts after enabling the embedded voltage regulator. It is mandatory to wait for a stable 3V3 supply input to the voltage regulator before enabling it.

The crystal oscillator starts automatically after VDDCORE is stable; it takes a maximum of 2 ms to get stable operation. The NRST pin must be tied to ‘0’ during crystal oscillation startup, and it must be released to ‘1’ after at least 32 Xtal clock periods. The clock signals will start operation ≈290 µs after NRST release. Then the external host CPU will access Bootloader logic to transfer the program and release the system for operation.

Figure 11-2. Power On Timing Diagram

Timing between ENABLE active and NRST release must always be greater than {150µs + 2ms + 32Txtal} as shown in the previous figure.

Although no special power-up sequence is required between high-voltage PVDDAMP power domain and low-voltage domain (VDDIO, VDDIN and VDDAMP), it is recommended to satisfy the ramp-up slopes defined in Table 5-2.