4.4.3.5 ID Check

ID Check Overview

The ID check module can compare predefined IDs with the first bytes of the received data payload. If a match occurs, this is indicated in a single register bit. The ID can have a length of 1, 2, 3 or 4 bytes and an offset from the beginning of the data payload of 0, 1, 2 or 3 bytes. The block is controlled by an internal finite state machine.

The following figure shows a block diagram of the ID check module.
Figure 4-14. ID Check Block Diagram

To initiate an ID check, the required ID must first be written to the ID byte registers IDB0, IDB1, IDB2 and IDB3. An ID can, therefore, have a length of 1, 2, 3 or 4 bytes and must be configured in the IDC.IDL register. If the ID is not located at the very beginning of the data payload, a byte-wise offset of up to 3 bytes can be configured in IDC.IDBO.

Before the ID check is started, the user must ensure that at least the IDC.IDBO + IDC.IDL payload bytes have been received, because otherwise the ID check will fail.

The user can enable an ID buffer full interrupt by setting IDC.IDFIM to ‘1’. This triggers an interrupt to the AVR after 7 bytes are received, which is the worst case scenario (ID length of 4 bytes and 3 bytes offset). The interrupt can be used by the software to start an ID check with any configuration regardless of the length and offset values of the actual ID. Instead of using the interrupt, the IDS.IDFULL flag can be polled.

After the configuration is complete, the ID check can be started by setting IDC.IDCE to ‘1’. It is permitted to write IDCE together with IDBO and IDL in one write access to the IDC register. The result is available within one clock cycle and written to IDS.IDOK. A ‘1’ marks a successful ID check. The bit is only cleared by a module reset or by writing a ‘1’ to it, but not by a successive negative ID check. This functionality allows an arbitrary number of IDs to be processed in a row, and checking afterward if at least one match occurred.

The ID check is reset when activated in the corresponding PRR2.PRIDS power reduction register or by writing a ‘1’ to the IDC.IDCLR bit. See Sleep Modes and Active Power Reduction from Related Links.

For more details on the description of the required register bits, see ID Check Register Description from Related Links.