4.3.6 Fractional-N PLL Register Overview
The PLL uses the following registers. The application software must not change the RF front-end register (see the following table). The firmware uses them to control the start-up, power-down and calibration of the fractional-N PLL.
Register | Function |
|---|---|
FESR.PLCK | PLL locked |
FEEN1.PLSP1 | PLL speed-up |
FEEN1.PLCAL | PLL Calibration mode |
FEEN1.PLEN | PLL enable |
FEEN2.PLPEN | PLL post enable |
FECR.PLCKG | PLL lock detect gate |
FEVCT.FEVCT[3:0] | RF front-end VCO tuning register |
The RF front-end values are transferred from the factory-locked EEPROM to the RF front-end by firmware before using the PLL (see the following table).
Register | Function |
|---|---|
FEBT.RTN2[1:0] | Resistor tuning |
FEBT.CTN2[1:0] | Capacitor tuning |
FETN4.CTN4[3:0] | Capacitor tuning |
FETN4.RTN4[3:0] | Resistor tuning |
FEVCO.VCOB[3:0] | VCO bias 4-bit value(1) |
FEVCO.CPCC[3:0] | Charge pump current control(1) |
Note:
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The RF front-end registers from RF Front-end Registers used by Firmware are changed due to application-specific settings coming from the EEPROM. See RF Front-end Registers used by Firmware in the Fractional-N PLL Register Overview from Related Links. Use the configuration tool must to calculate these EEPROM settings. In the configuration tool, modify the FFREQ settings to compensate both the initial XTO and the XTAL frequency tolerances. Consider the exact frequency steps of the PLL (fXTO/218 = 92.7 Hz in Low-band frequency range and fXTO/217 = 185.43 Hz in High-band when using a 24.3 MHz crystal).
Register | Function |
|---|---|
FEMS.M[3:0] | Main counter |
FEMS.S[3:0] | Swallow counter |
FECR.S4N3 | Select 433MHz/315MHz band |
FECR.LBNHB | Select Low-/High-band |
FEVCO.VCOB[3:0] | VCO bias (1) |
FEVCO.CPCC[3:0] | Charge pump current control (1) |
Note:
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