4.3.2 PFD/CP and Loop Filter

The PFD/CP and the loop filter compare the output frequency of the fractional divider f_DIV with the reference frequency f_XTO in phase domain and adjust the control voltage of the VCO resulting in f_DIV = f_XTO.

To obtain stable dynamic behavior of the PFD/CP and loop filter over production, the following preprogrammed calibration values must be set before the analog PLL loop is used: FEBT.RTN2[1:0], FEBT.CTN2[1:0], FETN4.CTN4[3:0] and FETN4.RTN4[3:0], which control the resistors and capacitors in the loop filter. In addition, the complete loop is controlled by the charge pump current using FEVCO.CPCC[3:0]. See RF Front-end Registers for Factory Locked Calibration in the Fractional-N PLL Register Overview from Related Links.

Two parameters can be used to calculate the FEVCO.CPCC[3:0] value. The first parameter comes from the factory-locked EEPROM, which compensates for the process tolerances. The second one is calculated based on the actual output frequency and is stored in the EEPROM settings for each service. The configuration tool must be used to calculate the necessary EEPROM settings for each service in use.