4.3.1 Overview

The preceding figure shows the block diagram of the fractional-N PLL. It consists of a Phase Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LF), a Voltage Controlled Oscillator (VCO), an RF divider, a fractional divider and a Sigma Delta Modulator (SDM). The reference frequency f_XTO, which is used for the PLL, is the output of the XTO.

In RXMode, the PLL is used to generate the local oscillator signal with the frequency of f_LO for the mixer. The PLL is able to cover the frequency bands of 310 MHz to 318 MHz, 418 MHz to 477 MHz (Low-band) and 836 MHz to 956 MHz (High-band).

The tolerances of the PLL are minimized by means of calibration. The calibration data is stored in the factory-locked EEPROM section and written by firmware into the front-end registers. See Fractional-N PLL Register Overview from Related Links. The dynamic transfer function of the PLL is, thus, very stable. The locking time of the PLL is very constant due to calibration.

During start-up, activate an additional speed-up mode (register bit FEEN1.PLSP1) to achieve shorter locking times.

A lock detect circuit, enabled with the register bit FECR.PLCKG, delivers a lock status in the FESR.PLCK register bit. Based on this information, the software can ensure that the ATA8210/15 does not start up a Receive mode if the PLL is not locked.

Use a Sigma Delta Modulator (SDM) to dither the fractional spurious in a way that the resulting pseudo random noise is below the phase noise of the VCO. The frequency resolution of the output frequencies (f_LO) is f_XTO / 2¹⁸ = 92.7 Hz in the Low-band frequency range and f_XTO / 2¹⁷ = 185.4 Hz in the High-band frequency range when using a 24.3 MHz crystal.