4.8.1 Overview

The Sequencer State Machine (SSM) implements major control parts to set up and run the receive operations. It makes the start-up and shutdown process more robust and predictable because it is not susceptible to timing deviations as if controlled by the AVR core with a varying workload.

To set up a reception, the software initially needs to load the configuration, such as the filter settings and frequency parameters to the corresponding hardware registers. Afterward, it hands over the control to the SSM that enables all required blocks with an appropriate timing, taking into account the settling times of filters and analog components.

The configuration of the SSM offers some flexibility such as deciding whether VCO tuning is needed or not. The start-up flows are broken up into smaller elements, allowing parts of the SSM functionality to be used only. In addition, the start-up flows augment software-controlled sequences.

The integrated dedicated VCO tuning timer frees other on-chip resources for application use.

The following figure shows a diagram of useful sub-state-machine sequences. The system needs to be in the IDLEMode(XTO) with the RF front end powered up and the system running on clk_XTO.

Several state machines are needed to transition between the three shown states of IDLEMode(XTO) and RXMode. The flow may be interrupted between every sub-state machine to intersperse some user software code. Other orders of sub-state machines than those shown in the diagram are prohibited.

The following figure shows the standard sequence for initializing the system for RF reception. The optional VCO tuning sub-state machine is marked in light gray.

The following figure illustrates the standard sequence for initializing the system. Here, the VCO tuning sub-state machine is optional.

When the RF channel is switched during reception, it needs to be ensured that the PLL has settled to the new frequency. A new PLL lock sequence is, thus, required if one of the following conditions is true:

• A VCO tuning occurred
• High-band/Low-band switching (FECR.LBNHB modification)
• Modification of the FEMS.PLLM or FEMS.PLLS values
• Modification of the MSB in the FFREQ1H or FFREQ2H register
• Modification of the PLL frequency by more than 1 MHz

The RX-to-RX switching sequence is realized (see the following figure). Once the RX DSP is stopped, the PLL lock sub-state machine waits for the lock signal of the PLL, and the RX DSP is enabled again while running on the new frequency.

The user must activate SSM in the corresponding power reduction register PRR2.PRSSM. See Sleep Modes and Active Power Reduction from Related Links.