4.8.4 PLL Lock State Machine

The PLL lock state machine activates the PLL speed-up mode for faster locking, then waits for the PLL lock signal. The necessary sequence to read the lock flag is passed a maximum of three times. If no lock is reached by that point, the state machine ends with the error flag set.

This state machine enables the ADC and the IF amplifier depending on the settings available in Settings Influencing the PLL Enable State Machine. See Settings Influencing the PLL Enable State Machine in the PLL Enable State Machine from Related Links.

After having successfully passed the PLL lock state machine, the RF must be up and running and the design can be put into RXMode by starting the RX DSP enable state machine.