AN5188

3.3 Clocking Structure

The design uses the following on-board clocks:

The 27 MHz oscillator is used to provide a reference clock to PF_CCC_C0
The on-board 50 MHz clock, which is driven as DDR Reference Clock, Processor Sub System, and UART Interface
The XCVR TX PLL subsystem generates a bit clock and XCVR receives
The LANE0_RX_CLK_R XCVR Clock provides a reference clock to PF_CCC_C3 and generates 59.4 MHz

The following figure shows the clocking structure of the design.

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