3.2 I/O Ports
(Ask a Question)The following table lists the important I/O ports of the design.
Port Name | Direction | Description |
---|---|---|
LANE0_RXD_N | Input | Lane0 RX channel N |
LANE0_RXD_P | Input | Lane0 RX channel P |
LANE1_RXD_N | Input | Lane1 RX channel N |
LANE1_RXD_P | Input | Lane1 RX channel P |
LANE2_RXD_N | Input | Lane2 RX channel N |
LANE2_RXD_P | Input | Lane2 RX channel P |
LANE3_RXD_N | Input | Lane3 RX channel N |
LANE3_RXD_P | Input | Lane3 RX channel P |
LANE4_RXD_N | Input | Lane4 RX channel N |
LANE4_RXD_P | Input | Lane4 RX channel P |
LANE5_RXD_N | Input | Lane5 RX channel N |
LANE5_RXD_P | Input | Lane5 RX channel P |
LANE6_RXD_N | Input | Lane6 RX channel N |
LANE6_RXD_P | Input | Lane6 RX channel P |
LANE7_RXD_N | Input | Lane7 RX channel N |
LANE7_RXD_P | Input | Lane7 RX channel P |
LANE0_TXD_N | Output | Lane0 TX channel N |
LANE0_TXD_P | Output | Lane0 TX channel P |
LANE1_TXD_N | Output | Lane1 TX channel N |
LANE1_TXD_P | Output | Lane1 TX channel P |
LANE2_TXD_N | Output | Lane2 TX channel N |
LANE2_TXD_P | Output | Lane2 TX channel P |
LANE3_TXD_N | Output | Lane3 TX channel N |
LANE3_TXD_P | Output | Lane3 TX channel P |
REF_CLK_PAD_N | Input | Reference clock N |
REF_CLK_PAD_P | Input | Reference clock P |
CLK_IN | Input | 27 MHZ of CLK |
RX | Input | RX for UART Interface |
TCK | Input | TCLK for Flash Pro Debug |
TDI | Input | TDI for Flash Pro Debug |
TMS | Input | TMS for Flash Pro Debug |
TSRTB | Input | TSRTB for Flash Pro Debug |
SLVS_EC_XCE | Output | Serial Communication Interface XCE Pin for i2c (Fixed to HIGH) |
SLVS_EC_XMASTER | Output | Master/Slave Select (Slave Mode: HIGH, Master Mode: LOW) |
SLVS_EC_RSTN | Output | SLVS Camera Reset |
CLK_50MHZ | Input | 50 MHz of On Board Clock |
TDO | Output | TDO for Flash Pro Debug |
SLVS_SCL | Input and Output | SLVS Cam I2C SCL |
SLVS_SDA | Input and Output | SLVS Cam I2C SDA |
GPIO_OUT_0[3:0] | Output | GPIO_OUT_0 is connected to LED0, 1, 2, 3. |
TX | Output | Tx for UART Interface |