3 Design Description

The following figure shows a high-level block diagram of the design.

Figure 3-1. Block Diagram
The following steps outline the preceding block diagram:
  1. The IMX-530 SLVS FMC captures video data through the transceiver (XCVR), passes it to the Core PCS, and finally routes it to the SLVS-EC Rx IP.
  2. The SLVS-EC Rx IP decodes the SLVS-EC format and generates RAW pixel output, which is stored in the DDR memory as a video frame (consisting of PolarFire® DDR4, DDR Write, DDR Read, and DDR Arbiter).
  3. The Raw video frame is read back and processed through the video pipeline consisting of Bayer interpolation, Gamma correction, and Image enhancement.
  4. The processed video is streamed over HDMI output by using Display Controller and HDMI 2.0 Tx IP.
  5. This design also integrates a separate processing block, the PROC_SUB_SYSTEM, which is responsible for initializing the IMX-530 camera through the I2C interface.