3.1 Hardware Implementation

The following figure shows the Libero SoC implementation of the top-level SmartDesign.

Figure 3-2. High-Level SLVS-EC Design

The SLVS-EC design includes the following key blocks:

  • HDMI_2P0_FHD_TX (TX_PLL, HDMI 2.0 TX, and XCVR)
  • Video_Pipelining_Block (DDR Write, DDR Read, DDR AXI4 Arbiter, and Display Controller)
  • IMX_TOP (SLVS-EC RX, Core PCS, and XCVR)
  • Video Processing Block (Bayer_Interpolation, Gamma_Correction, and Image_Enhancement)
  • PF_DDR4
  • PROC_SS (MIV_RV32, CoreGPIO, PF_SRAM_AHBL_AXI, and COREI2C)
  • UART Interface (COREUART)

XCVR Configuration -1

The transceiver configuration for HDMI Tx implementation is shown in the following figure. The transceiver is configured in Tx only mode in 4 lane configuration. The clock signal is carried by LANE0, while lanes 1, 2, and 3 carry the blue, green, and red video signals. The transceiver is configured for Full High Definition (FHD) which is 1920 x 1080p at 60 frames per second. This configuration is labeled as XCVR Configuration -1, as shown in the following figure.

Figure 3-3. XCVR Configuration -1

XCVR Configuration -2

The SLVS-EC Rx is configured to operate in an 8-lane mode and hence, 8-transceiver Rx-lanes are required to receive the video data. The PolarFire FPGA implements transceiver lanes grouped in quads, each consisting of four lanes. Hence, two transceiver quads are used to implement 8-lane configuration. Both the quads use the same configuration as shown in the following figure.

Figure 3-4. XCVR Configuration -2

CorePCS Configuration

CorePCS consists of a user interface and a transceiver interface. The user interface includes transmit and receive data functionalities, along with various control and status signals that qualify the data. The Core PCS IP in the design, the LANE_MODE is set to Receiver Only with EPCS_Data_Width as 40 bit, Comma(s) to detect is configured as “K28.5”, and No. of commas is configured to “1”, as shown in the following figure.
Figure 3-5. CorePCS Configuration

SLVS-EC Rx IP Configuration

SLVS-EC Rx IP has the following configuration options:
  • DATA WIDTH has configuration options as Raw 8, Raw 10, and Raw 12
  • LANE WIDTH has configuration options as two lanes, four lanes, and eight lanes
  • Video Interface has configuration options as Native and AXI4 Stream

For more information about SLVS-EC Rx IP, see UG0877: SLVS-EC Receiver for PolarFire FPGA user guide.

The SLVS-EC Rx IP is configured with a native interface, which uses a Raw 8 configuration and a 8-lane width.
Figure 3-6. SLVS-EC Rx IP Configuration using Raw 8 and 8-Lane Width for Native Interface

HDMI TX IP Configuration

HDMI Tx IP core is configured in Single bit mode for native interface. HDMI Tx IP encodes video, auxiliary, and control data to Transition-minimized Differential Signaling (TMDS) data, which pass through transceiver.

Figure 3-7. HDMI TX 2.0 IP Configuration using Single-bit Mode for Native Interface