3.4 Reset Structure
(Ask a Question)The SLVS-EC design is initialized upon the de-assertion of the DEVICE_INIT_DONE signal from the PF_INIT_MONITOR block, along with the XCVR_INIT_DONE signal from the same block. In addition to this primary reset, the design incorporates three additional resets, each synchronized with a specific clock. The first reset, DDR_Write_reset, resets the DDR write operations and is synchronized with the clock from the SLVS-EC Rx IP. The second reset, Video processing reset, resets all the video processing IP and display controller IP, using the 148.5 MHz clock. The third reset, DDR_SYSTEM_reset, resets DDR read and arbiter operations, as well as other reset operations, utilizing the clock from the onboard 27 MHz source.
The following figure shows the reset structure of the design.
